The present invention generally relates to transistors and more particularly, to a thin film transistor (referred to as "TFT", hereinbelow) array which has a structure leading to an improvement of yield of its manufacture.
Recently, in active matrix display of liquid crystal, an extensive study has been conducted on an active matrix substrate in which TFTs are formed in a shape of a matrix on an insulating substrate. Semiconducting materials used for the TFTs include poly-Si, a(amorphous)-Si, Te, CdSe, etc.
A structure of a known TFT utilizes a-Si is described with reference to FIGS. 1 and 2. The known TFT includes a glass substrate 1 and a gate bus bar 3 for connecting gate electrodes 2 on the glass substrate 1. The gate bus bar 3 has a film thickness of 1,000 to 4,000 .ANG. and is made of such metals as Ta, Mo, Ti, Al, etc. A gate insulating film 4, which is stacked on the glass substrate 1 and the gate electrode 2, has a film having a film thickness of 1,000 to 3,000 .ANG.and is made of silicon nitride (referred to as "SiNx", hereinbelow) by using a plasma CVD (chemical vapor deposition) method. In FIG. 1, the gate insulating film 4 is not shown. An a-Si layer 5 acting as a semiconducting layer for the TFT , which is stacked on the gate insulating film 4, is formed into a film thickness of 100 to 3,000 .ANG., by using the plasma CVD method. A second insulating film 6, which is formed by SiNx film having a thickness of 1,000 to 5,000 .ANG., is formed on the a-Si layer 5 by using the plasma CVD method. Source electrodes 7 and a source bus bar 8 for connecting the source electrodes 7 are formed at right angles to the gate bus bar 3. The source bus bar 8 has a plurality of branch portions 8a arranged at predetermined intervals. Each of the TFTs is so formed as to be disposed, at its center, at each of the branch portions 8a. The source electrode 7 and a drain electrode 9 each have a film thickness of 2,000 to 10,000 .ANG. and are made of such metals as Mo, Ti, Al, etc.
Meanwhile, it is desirable that an a-Si film 10 having a thickness of 100 to 1,000 .ANG., in which phosphorus is doped, is disposed between the drain electrode 9 and the a-Si layer 5 because ohmic contact between the source electrode 7 and the a-Si layer 5 and between the drain electrode 9 and the a-Si layer 5 is effected. Thus, the TFTs are formed in a shape of an array at points of intersections between the gate bus bars 3 and the source bus bars 8. Furthermore, a picture element electrode 11, which is formed by a transparent and electrically conductive film made of, for example, indium oxide, is formed in contact with the drain electrode 9.
In the known active matrix substrate employing the TFT array, each point of intersection of the matrix is driven by a linear sequential method. Namely, a scanning signal is inputted from one gate bus bar to be scanned and a data signal is inputted from each source bus bar. A number of points of intersection are formed between the gate bus bars and the source bus bars. For example, in a matrix of 250.times.250, 62,500 points of intersection exist between the gate bus bars and the source bus bars. If a leakage occurs between a gate and a source even at one of the many points of intersection between the gate bus bars and the source bus bars, a cruciform line defect is necessarily produced between the corresponding gate bus bar and the corresponding source bus bar at the time of display, so that the display cannot be put to practical use. Thus, the yield of the active matrix substrate becomes zero. Therefore, as the number of gate bus bars and source bus bars increases, insulation between the gates and the sources is required to be performed with greater effect to reduce the likelihood of leakage.
As a result of investigation of the portions of leakage between the gates and the sources by using various methods, the present inventors have found that leakage takes place especially frequently at an intersectional portions (interrupted hatched portion in FIG. 1) between an edge of the gate and the source. It is considered that since the film thickness of the gate insulating film is larger than or substantially equal to that of the gate electrode, the gate bus bar has, at its edge portion, a smaller film thickness so as to have a smaller dielectric strength. Also because a stepped portion of the gate insulating film is inferior, in insulating property, to a flat portion of a the gate insulating film due to difference in the film properties between the flat portion and the stepped portion that causes this leakage.
A structure of another prior art field effect type TFT utilizes a-Si is described with reference to FIGS. 3 and 4. The prior art TFT includes an insulating substrate 410 made of glass or the like and a gate electrode 401 having a thickness of 1,000 to 4,000 .ANG.. Furthermore, by using the plasma CVD method, a gate insulating film having a thickness of 1,000 to 3,000 .ANG., an a-Si film 403 having a thickness of 100 to 3,000 .ANG. and a protective insulating film 404 having a thickness of 1,000 to 5,000 .ANG. are continuously stacked one upon another in a vacuum. Subsequently, after the protective insulating film 404 has been subjected to patterning, an n.sup.+ -a-Si film 405 having a thickness of 100 to 1,000 .ANG., that is phosphorus doped, and a source/drain metallic film 406 are stacked. By patterning the source/drain metallic film 406, the source/drain metallic film 406 is formed into a source electrode 407 and a drain electrode 408. It is to be noted that the protective insulating film 404 is provided for protecting the a-Si film 403 from etchant at the time of patterning of the n.sup.+ -a-Si film 405. Moreover, although not specifically shown, a picture element electrode is formed in contact with the drain electrode 408. Thus, the TFTs and the picture elements are formed in a shape of an array at points of intersection between the gate electrodes 401 and the source electrodes 407.
However, in the prior art TFT referred to above, such a problem arises in that the gate insulating film 402 having a thickness of 1,000 to 3,000 .ANG., which is made of SiO.sub.2, SiNx, etc., is readily damaged by hydrofluoric acid in processes for etching the n.sup.+ -a-Si film or the a-Si film, the source/drain electrode, etc. by using etchant including hydrofluoric acid, with no doping being performed in the a-Si film, the source/drain electrode, etc. Especially, at an edge portion of the gate electrode 401, the gate insulating film 402 not only has a smaller film thickness but is likely to be damaged by hydrofluoric acid due to its film properties. Hence, at encircled portions in FIG. 3, i.e., at intersectional portions between the edge portion of the gate electrode and the edge portion of the source/drain electrode, the gate insulating film 402 is damaged by hydrofluoric acid, so that a dielectric strength of the gate insulating film 402 drops and thus, undesirable leakage between the gate and the source is likely to take place.